Modern digital signal processors (DSP) faces multiple challenges. Workloads continue to increase, requiring increasing bandwidth. Systems on a chip (SOC) continue to grow in size and complexity. Memory system latency severely impacts certain classes of algorithms. As transistors get smaller, memories and registers become less reliable. As software stacks get larger, the number of potential interactions and errors becomes larger.
Memory bandwidth and scheduling are a problem for digital signal processors operating on real time data. Digital signal processors operating on real time data typically receive an input data stream, perform a filter function on the data stream (such as encoding or decoding) and output a transformed data stream. The system is called real time because the application fails if the transformed data stream is not available for output when scheduled. Typical video encoding requires a predictable but non sequential input data pattern. Often the corresponding memory accesses are difficult to achieve within available address generation and memory access resources. A typical application requires memory access to load data registers in a data register file and then supply to functional units which perform the data processing.